BQ20Z45 Datasheet, PDF (6/20 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge and Protection Enabled With Impedance Track™

bq20z45
SLUS800 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_(REG25) = 2.41 V to 2.59 V,
V_(BAT) = 14 V, C_(REG25) = 1 µF, C_(REG33) = 2.2 µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
I_(REG33MAX)
Current Limit
drawing current until REG33 = 3 V
short REG33 to VSS, REG33 = 0 V
25
100
145
12
65
THERMISTOR DRIVE
V_(TOUT)
Output voltage
R_DS(on)
TOUT pass element resistance
VCELL+ HIGH VOLTAGE TRANSLATION
I_(TOUT) = 0 mA; T_A = 25°C
I_(TOUT) = 1 mA; R_DS(on) = (V_(REG25) -
V_(TOUT) )/ 1 mA; T_A = –40°C to 100°C
V_(REG25)
50
100
V_(VCELL+OUT)
V_(VCELL+REF)
V_(VCELL+PACK)
V_(VCELL+BAT)
CMMR
Translation output
Common mode rejection ratio
VC(n) - VC(n+1) = 0 V;
T_A = –40°C to 100°C
VC(n) - VC(n+1) = 4.5 V;
T_A = –40°C to 100°C
internal AFE reference voltage ;
T_A = –40°C to 100°C
Voltage at PACK pin;
T_A = –40°C to 100°C
Voltage at BAT pin;
T_A = –40°C to 100°C
VCELL+
0.950
0.275
0.965
0.98 ×
V_(PACK)/18
0.98 ×
V_(BAT)/18
40
0.975
1
0.3
0.375
0.975
0.985
V_(PACK)/18
1.02 ×
V_(PACK)/18
V_(BAT)/18 1.02 × V_(BAT)/18
K
Cell scale factor
K= {VCELL+ output (VC5=0V;
VC4=4.5V) - VCELL+ output (VC5=0V;
VC4=0V)}/4.5
K= {VCELL+ output (VC2=13.5V;
VC1=18V) - VCELL+ output
(VC5=13.5V; VC1=13.5V)}/4.5
0.147
0.147
0.150
0.150
0.153
0.153
I_(VCELL+OUT)
Drive Current to VCELL+ capacitor
VC(n) - VC(n+1) = 0V; VCELL+ = 0 V;
T_A = –40°C to 100°C
12
18
V_(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) -
CELL output (VC2 = VC1 = 0 V)
-18
-1
18
I_VCnL
VC(n) pin leakage current
CELL BALANCING
VC1, VC2, VC3, VC4, VC5 = 3 V
-1
0.01
1
R_(BAL)
internal cell balancing FET resistance
R_DS(on) for internal FET switch at
V_DS = 2 V; T_A = 25°C
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T_A = 25°C (unless otherwise noted)
V_(OL)
OL detection threshold voltage
accuracy
V_OL = 25 mV (min)
V_OL = 100 mV; RSNS = 0, 1
V_OL = 205 mV (max)
V_(SCC)
SCC detection threshold voltage
accuracy
V_(SCC) = 50 mV (min)
V_(SCC) = 200 mV; RSNS = 0, 1
V_(SCC) = 475 mV (max)
V_(SCD)
SCD detection threshold voltage
accuracy
V_(SCD) = –50 mV (min)
V_(SCD) = –200 mV; RSNS = 0, 1
V_(SCD) = –475 mV (max)
t_da
Delay time accuracy
t_pd
Protection circuit propagation delay
FET DRIVE CIRCUIT; T_A = 25°C (unless otherwise noted)
V_(DSGON)
DSG pin output on voltage
V_(DSGON) = V_(DSG) - V_(PACK);
V_(GS) = 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
V_(CHGON)
CHG pin output on voltage
V_(CHGON) = V_(CHG) - V_(BAT);
V_(GS) = 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
V_(DSGOFF)
DSG pin output off voltage
V_(DSGOFF) = V_(DSG) - V_(PACK)
V_(CHGOFF)
CHG pin output off voltage
V_(CHGOFF) = V_(CHG) - V_(BAT)
200
15
90
185
30
180
428
–30
–180
–428
8
8
400
25
100
205
50
200
475
–50
–200
–475
±15.25
50
12
12
600
35
110
225
70
220
523
–70
–220
–523
16
16
0.2
0.2
UNIT
mA
V
Ω
V
dB
µA
mV
µA
Ω
mV
mV
mV
µs
µs
V
V
V
V
6
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