TMS320TCI6487_1 Datasheet, PDF (87/90 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 1.3, 1.2, 1.1, 1.0

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Silicon Revision 1.0 Known Design Exceptions to Functional Specifications
Note:
Care must be taken such that the software does not over-decrement the
counter since at the time of polling multiple requests may be in flight in
the system and may result in additional decrements compared to the
current observed value. If too many decrements occur, the counter may
roll under from 0x0 to 0x3F and accidentally result in saturation of the
counter. This is why a value of 0x20 is suggested as the threshold value
(sufficiently large with respect to the number of actual requests that may
be outstanding).
This workaround requires that a specific TC instance is dedicated to the COMPACTV
decrement transfer. The reason is that, depending on the nature of the traffic on a given
queue/TC, it may be difficult to control the timing of the normal CC TR submission to that
TC versus the DSP programming of that TC. There is no hardware protection to prevent
corruption of the TC registers in the case that both CC and DSP software attempt to
program the TC simultaneously.
For the base addresses of the TCs, see the device-specific data manual,
TMS320TCI6487/8 Communications Infrastructure Digital Signal Processor (literature
number SPRS358). A brief summary of the TC registers to be configured are provided in
Table 12.
ADDRESS
TCx Base + 0x0200
TCx Base + 0x0204
TCx Base + 0x0208
TCx Base + 0x020C
TCx Base + 0x0210
Table 12. TC Registers Summary
REGISTER
DESCRIPTION
Prog Set Options
Prog Set Src Address
Prog Set Count
Prog Set Dst Address
Prog Set B-Dim Idx
SUGGESTED VALUE
See the Prog Set Options Register description below
See Prog Set Src/Dst Address Register description
below
0x00010004 (ACNT = 4 and BCNT =1)
See Prog Set Src/Dst Address Register description
below
0x0 (don't care since BCNT=1). Writing to the PBIDX
register triggers the transfer. Thus, this register
should be written.
Note: The five registers listed in Table 12 should be written in the sequence shown (i.e.,
top to bottom). The last write, to the Prog Set B-Dim Idx register, triggers the transfer.
Prog Set Options Register
The Prog Set Option register is shown in Figure 12. The TCINTEN bit should be set to
0x1. The TCC code should be set to some known value that is not used by other
requests in the system. The other fields should be set to 0x0. Upon completion of the
transfer, the TCC value will be set in the corresponding bit in the IPR/IPRH registers.
The software should poll for this bit in the IPR/IPRH registers and then clear it with the
ICR/ICRH registers before programming the next COMPACTV decrement transfer.
Figure 12. Prog Set Options Register
31
23
22
21
20
19
18
17
16
Reserved
TCCH
_EN
Rsvd
TCINT
_EN
Reserved
TCC
R-0
R/W-0 R-0 R/W-0
R-0
R/W-0
15
12
11
10
8
TCC
Rsvd
FWID
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
Rsvd
R-0
6
4
PRI
R/W-0
3
2
Reserved
R-0
1
0
DAM SAM
R/W-0 R/W-0
SPRZ248D – September 2007 – Revised August 2008
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TMS320TCI6487/8 DSP
87
Silicon Revisions 1.3, 1.2, 1.1, 1.0