TMS320TCI6487_1 Datasheet, PDF (14/90 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 1.3, 1.2, 1.1, 1.0

Silicon Revision 1.3 Known Design Exceptions to Functional Specifications
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Method 3
Entirely eliminate the exception by removing all SDMA/IDMA accesses to L2 SRAM. For
example, EMAC descriptors and EMAC payload cannot reside in L2. Master peripherals
like the EDMA/QDMA, IDMA, and SRIO cannot access L2. There are no issues with the
CPU itself accessing code/data in L2. This issue only pertains to SDMA/IDMA accesses
to L2.
Deadlock Avoidance
To avoid the manifestation of a C64x+ deadlock, several Workarounds: are suggested
depending on the VBUSM master in question:
VBUSM MASTER
GEM
EDMA3TCx
EMAC
SRIO
SRIO CPPI
RAC Back End 0
RAC Back End 1
WORKAROUND
GEMs should not write to the memory of any other GEM. This will cause
complications across any master peripheral that is transferring data to multiple
L2s. GEMs must not directly read from the memory of any other GEMs without
providing the L1D cache disable workaround mentioned in Method 2 to ensure
that the load will not stall itself indefinitely and hang the system.
Inbound and outbound traffic should be programmed on different TC ports (i.e.,
two different EDMA queues, since a given queue maps to a given TC). Note that
in-/out-bound direction is defined as the write direction, meaning that a
DDR2-to-DDR2 transfer is outbound and L2-to-L2 is inbound. Any TC used to
write to DDR should not be used to write to a GEM even when the TC writing to
the DDR is also reading from DDR.
EMAC should write to the GEM's memory or the DDR, but not both. This includes
buffers and buffer descriptors. EMAC CPPI descriptors should be placed wholly
in the local wrapper memory, any combination of wrapper and L2 memory (must
match other master transactions), or any combination of wrapper and DDR2
SDRAM (must match other master transactions). Buffer descriptors should not be
placed in any combination of L2 and DDR2 SDRAM.
SRIO should transfer payload data to only GEM memories or to DDR2 SDRAM,
but not both. This includes any direct I/O writes as well as any inbound RX
messaging transfer.
SRIO CPPI descriptors should be placed wholly in the local wrapper memory,
any combination of wrapper and L2 memory, or any combination of wrapper and
DDR2 SDRAM. Buffer descriptors should not be placed in any combination of L2
and DDR2 SDRAM.
RAC Back End 0 should transfer payload data to only the DDR or to the GEM,
but not both (no dependency on RAC Back End 1).
RAC Back End 1 should transfer payload data to only DDR or to GEM, but not
both (no dependency on RAC Back End 0).
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TMS320TCI6487/8 DSP
Silicon Revisions 1.3, 1.2, 1.1, 1.0
SPRZ248D – September 2007 – Revised August 2008
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