TMS320TCI6487_1 Datasheet, PDF (30/90 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 1.3, 1.2, 1.1, 1.0

Silicon Revision 1.2 Known Design Exceptions to Functional Specifications
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• Protect non-cacheable reads from generating an SDMA stall by freezing the L1D
cache during the non-cacheable read access(es). The following example code
contains a function that protects non-cacheable reads, avoids blocking during the
reads, and, therefore, avoids the deadlock state.
;; ======================================================================== ;;
;; Long Distance Load Word
;;
;;
;;
;;
int long_dist_load_word(volatile int *addr)
;;
;;
;;
;; This function reads a single word from a remote location with the L1D ;;
;; cache frozen. This prevents L1D from sending victims in response to ;;
;; these reads, thus preventing the L1D victim lock from engaging for the ;;
;; corresponding L1D set.
;;
;;
;;
;; The code below does the following:
;;
;;
;;
;;
1. Disable interrupts
;;
;;
2. Freeze L1D
;;
;;
3. Load the requested word
;;
;;
4. Unfreeze L1D
;;
;;
5. Restore interrupts
;;
;;
;;
;; Interrupts are disabled while the cache is frozen to prevent affecting ;;
;; the performance of interrupt handlers. Disabling interrupts during
;;
;; the long distance load does not greatly impact interrupt latency,
;;
;; because the CPU already cannot service interrupts when it's stalled by ;;
;; the cache. This function adds a small amount of overhead (~20 cycles) ;;
;; to that operation.
;;
;;
;;
;; ======================================================================== ;;
.asg 0x01840044,
L1DCC
.global _long_dist_load_word
.text
.asmfunc
; int long_dist_load_word(volatile int *addr)
_long_dist_load_word:
MVKL L1DCC,
B4
MVKH L1DCC,
B4
||
DINT
||
MVK
1,
B5
STW
B5,
*B4
LDW
*B4,
B5
NOP
4
SHR
B5,
16,
B5
||
LDW
*A4,
A4
NOP
4
STW
B5,
*B4
RET
B3
||
LDW
*B4,
B5
NOP
4
RINT
.endasmfunc
; L1D Cache Control
; Disable interrupts
; \_ Freeze cache
;/
; POPER -> OPER
; read value remotely
; \_ Restore cache
;/
; Restore interrupts
;; ======================================================================== ;;
;; End of file: ldld.asm
;;
;; ======================================================================== ;;
In the TCI6487/8 multicore device, when one GEM is accessing another GEM's L1 or L2
memory it is an MDMA access, so the potential SDMA/IDMA stall can occur. The stall
can be avoided by using the EDMA to transfer data from one GEM's memory to another.
30
TMS320TCI6487/8 DSP
Silicon Revisions 1.3, 1.2, 1.1, 1.0
SPRZ248D – September 2007 – Revised August 2008
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