TMS320TCI6487_1 Datasheet, PDF (48/90 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 1.3, 1.2, 1.1, 1.0

Silicon Revision 1.1 Known Design Exceptions to Functional Specifications
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SDMA/IDMA stalls may occur during the following scenarios. Each of these scenarios
describes expected normal DSP functionality, but the SDMA/IDMA access potentially
exhibits additional unexpected stalling.
1. Bursts of writes to non-cacheable MDMA space (i.e., DDR2). The DSP buffers up to
4 non-cacheable writes. When this buffer fills, SDMA/IDMA is blocked until the buffer
is no longer full. Therefore, bursts of non-cacheable writes longer than three writes
can stall SDMA/IDMA traffic.
2. Various combinations of L1 and L2 cache activity:
a. L1D read miss generating victim traffic to L2 (cache or SRAM) or external
memory. The SDMA/MDMA may be stalled while servicing the read miss and the
victim. If the read miss also misses L2 cache, the SDMA/IDMA may be stalled
until data is fetched from external memory to service the read miss. If the read
access is to non-cacheable memory there will still potentially be an L1D victim
generated even though the read data will not replace the line in the L1D cache.
b. L1D read request missing L2 (going external) while another L1D request is
pending. The SDMA/IDMA may be stalled until the external memory access is
complete.
c. L2 victim traffic to external memory during any pending L1D request. The
SDMA/IDMA may be stalled until external memory access and the pending L1D
request are complete.
The duration of the SDMA/IDMA stalls depends on the quantity/characteristics of the
L1/L2 cache and the MDMA traffic in the system. In cases 2a, 2b, and 2c, stalling may or
may not occur depending on the state of the cache request pipelines and the traffic
target locations. These stalling mechanisms may also interact in various ways, causing
longer stalls. Therefore, it is difficult to predict if stalling will occur and for how long.
SDMA/IDMA stalling and any system impact is most likely in systems with excessive
context switching, L1/L2 cache miss/victim traffic, and heavily loaded EMIF.
Use the following steps to determine if SDMA/IDMA stalling is the cause of real-time
deadline misses for existing applications. Situations where real-time deadlines may be
missed include loss of McBSP samples and low peripheral throughput.
1. Determine if the transfer missing the real-time deadline is accessing L2 or L1D
memory. If not, then SDMA/IDMA stalling is not the source of the real-time deadline
miss.
2. Identify all SDMA transfers to/from L2 memory (e.g., EDMA transfer to/from L2
from/to a McBSP or from/to AIF, TCP, or VCP). If there are no SDMA transfers going
to L2, then SDMA/IDMA stalling is not the source of the problem.
3. Redirect all SDMA transfers to L2 memory to other memories using one of the
following methods:
• Temporarily transfer all the L2 SDMA transfers to L1D SRAM.
• If not all L2 SDMA transfers can be moved to L1D memory, temporarily direct
some of the transfers to DDR memory and keep the rest in L1D memory. There
should be no L2 SDMA transfers.
• If neither of the above approaches are possible, move the transfer with the
real-time deadline to the EMAC CPPI RAM. If the EMAC CPPI RAM is not big
enough, a two-step mechanism can be used to page a small working buffer
defined in the EMAC CPPI RAM into a bigger buffer in L2 SRAM. The EDMA
module can be setup to automate this double buffering scheme without CPU
intervention for moving data from the EMAC CPPI RAM. Some throughput
degradation is expected when the buffers are moved to the EMAC CPPI RAM.
Note: Note that EMAC CPPI RAM memory is word-addressable only and,
therefore, must be accessed using an EDMA index of 4 bytes.
If real-time deadlines are still missed after implementing any of the options in Step 3,
then SDMA/IDMA stalling is likely not the cause of the problem. If real-time deadline
misses are solved using any of the options in Step 3, then SDMA/IDMA stalling is likely
the source of the problem.
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TMS320TCI6487/8 DSP
Silicon Revisions 1.3, 1.2, 1.1, 1.0
SPRZ248D – September 2007 – Revised August 2008
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