PCI1031 Datasheet, PDF (85/100 Pages) Texas Instruments – PCI-TO-PC CARD16 CONTROLLER UNIT

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT
SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997
DMA status/command register
Bit
7
6
5
4
3
2
1
0
Name
DMA status
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
DMA command
Type
R
R
R
R
R
R/W
R
R
Default
0
0
0
0
0
0
0
0
Register: DMA status/command
Type:
Read only, read/write (see individual bit descriptions)
Offset:
DMA base address + 08h
Default: 00h
Size:
One byte
Description: This address contains both the DMA status and command registers. During PCI I/O read
cycles to this address, the PCI1031 returns the contents of the DMA status register. During
PCI I/O write cycles to this address, the DMA command register is written. The DMA status
and command registers remain in accordance with the 8237 DMA controller register
definitions; however, certain bits are not implemented in the PCI1031. Refer to Table 45 for a
complete description of the status register contents and Table 46 for a complete description of
the command register contents.
Table 45. DMA Status Register
BIT TYPE
FUNCTION
Channel request. In the 8237 DMA controller, bits 7–4 indicate the status of the DREQ signal of each DMA channel. In
the PCI1031, the status register only reports information about a single DMA channel; therefore, all four of these register
7–4
R
bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card
asserts its DREQ signal and are reset when DREQ is high (deasserted). The status of the mask bit in the multichannel
mask register has no effect on these bits.
Channel TC. The 8237 DMA controller uses bits 3–0 to indicate the TC status of each of its four DMA channels. In the
3–0
R
PCI1031, the status register reports information about just a single DMA channel; therefore, all four of these register bits
indicate the TC status of the single socket being serviced by this register. All four bits are set when the TC is reached by
the DMA channel. Bits 3–0 are reset when read or when the DMA channel is reset.
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