PCI1031 Datasheet, PDF (36/100 Pages) Texas Instruments – PCI-TO-PC CARD16 CONTROLLER UNIT

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT
SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997
PCI configuration headers (continued)
Host software exerts control and retrieves status information on PC Cards via a standard set of internal PCI1031
registers: ExCA registers for 16-bit PC Cards. The PCI1031 maps these registers into PCI address space for
access by host software. The locations of these registers are set by the CardBus socket registers/ExCA
registers base address (see CardBus socket registers/ExCA registers base address register) register in PCI
configuration space, which locates a 4K-byte nonprefetchable memory window in PCI memory address space.
Within this memory window, the PCI1031 maps both the socket registers and the ExCA registers. Each socket
has a separate CardBus socket register/ExCA registers base address register for accessing the ExCA registers.
The 16-bit PC Cards use the ExCA register set for card status and control purposes. Traditionally, these
registers have been accessed by host software through an index/data register pair. Software would write the
index of the desired ExCA register to the index register, and read or write the desired data to the data register.
The PCI1031 departs from this scheme by directly mapping the ExCA register set to a 4K-byte memory window
located by the CardBus socket registers/ExCA registers base address register. The ExCA registers are offset
from this base address by 800h. The PCI1031 also supports the index/data scheme of accessing the ExCA
registers through the use of the PC Card 16-bit I/F legacy-mode base address register (see PC Card 16-bit I/F
legacy-mode base address). An address written to this register becomes the address for the index register and
the address+1 becomes the address for the data address. Using this access method, applications requiring
index/data type ExCA access can be supported. This PC Card 16-bit legacy-mode base address is shared by
both sockets and the ExCA registers run contiguously from offset 00h–3Fh for Socket A and 40h–7Fh for
socket B.
The PCI1031 implements two PCI configuration headers, one for each PC Card socket; therefore, all memory
and I/O window functionality for socket A are repeated, but separate from, socket B. Host software must
program nonoverlapping memory and I/O resources for each socket.
The TI extension registers are specific PCI1031 value-added features that are not part of currently defined PC
Card industry specifications. The TI extension registers are a collection of control and status bits that are
required to support various PCI1031 functions. These functions typically do not exist within the register models
implemented elsewhere within the device. Tables 11 and 12 show the TI extension registers and their locations
in PCI configuration space.
Table 11. TI Extension Registers
REGISTER NAME OFFSET
System control†
80h
Retry status†
90h
Card control†
91h
Device control†
92h
Test†
93h
† _{One or more bits in the register are}
common to PCI functions 0 and 1.
The PCI1031 supports the DMA specification defined in the 1995 PC Card standard by providing one DMA
channel per socket. The PC Card standard stipulates the signaling and timing associated with DMA transfers
to and from a PC Card. This defines DMA transfers from the PC Card to the socket only. On the PCI side, the
PCI1031 implements a set of status and control registers similar to the programming model of the original dual
8237 DMA controller found in PC-AT systems. These registers comply with the specification for distributed DMA
in a PCI environment, particularly as it defines DMA devices. The PCI1031 provides two registers in its
configuration header that set up both the PCI interface and PC Card socket for DMA. See PC Card DMA and
distributed DMA for a complete discussion of DMA support on the PCI1031.
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