PCI1031 Datasheet, PDF (37/100 Pages) Texas Instruments – PCI-TO-PC CARD16 CONTROLLER UNIT

PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT
SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997
PCI configuration headers (continued)
Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers.
Socket DMA register 0 applies to the PC Card portion of DMA transfers. Socket DMA register 1 applies to the
PCI portion of DMA transfers specifically to set up the DMA support required in distributed DMA. Socket DMA
register 1 provides register bits to program the DMA transfer width. This transfer width refers to both the PC Card
interface and the PCI interface.
Descriptions of each of the registers follow. Before writing data to any of the TI extension registers, host software
must first read the register to preserve the current contents. After reading the register, software can modify the
desired bits and write back the new data. This preserves current register settings and prevents unpredictable
or undesirable behavior.
The PCI1031 configuration header is shown in Table 12.
Table 12. PCI1031 Configuration Header
REGISTER NAME
Device ID
Vendor ID
Status
Command
BIST
Class code
Header type
Latency timer†
Revision ID
Cache line size†
CardBus socket registers/ExCA base-address register
Secondary status (unused)‡
Reserved
CardBus latency timer†
Subordinate bus number
CardBus bus number
CardBus memory base register 0 (unused)‡
CardBus memory limit register 0 (unused)‡
CardBus memory base register 1 (unused)‡
CardBus memory limit register 1 (unused)‡
CardBus I/O base register 0 (unused)‡
CardBus I/O limit register 0 (unused)‡
CardBus I/O base register 1 (unused)‡
CardBus I/O limit register 1 (unused)‡
Bridge control†
Interrupt pin
PCI bus number†
Interrupt line
Subsystem ID
Subsystem vendor ID
PC Card 16-Bit I/F legacy-mode base address†
Reserved
System control†
Test†
Reserved
Device control†
Card control†
Retry status†
Socket DMA register 0
Socket DMA register 1
Reserved
† _{One or more bits in the register are common to PCI functions 0 and 1.}
‡ _{Unused registers are read only.}
OFFSET
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h–7Ch
80h
84h–8Ch
90h
94h
98h
9Ch–FFh
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
37