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XIO3130 Datasheet, PDF (84/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express x1 3-port fanout switch
XIO3130
SLLS693C – MAY 2007 – REVISED JUNE 2008
www.ti.com
Table 4-47. Correctable Error Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
7
BAD_DLLP
rcuh
Bad DLLP error. This bit is asserted when an 8b/10n error is detected by the PHY during
reception of a DLLP.
6
BAD_TLP
rcuh
Bad TLP error. This bit is asserted when an 8b/10b error is detected by the PHY during
reception of a TLP.
5:1
RSVD
r
Reserved. Return zeros when read.
0
RX_ERROR
rcuh
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any
time.
4.2.82 Correctable Error Mask Register
The Correctable Error Mask register controls the reporting of individual errors as they occur. When a bit is
set to one, error status bits are still affected, but the error is not logged and no error reporting message is
sent upstream.
PCI register offset:
114h
Register type:
Read Only, Read/Write
Default value:
0000 2000h
BIT NUMBER
RESET STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31:14
13
12
11:9
8
7
6
5:1
0
FIELD NAME
RSVD
ANFEM
REPLAY_TMOUT_MASK
RSVD
REPLAY_ROLL_MASK
BAD_DLLP_MASK
BAD_TLP_MASK
RSVD
RX_ERROR_MASK
Table 4-48. Correctable Error Mask Register
ACCESS
r
rwh
rwh
r
rwh
rwh
rwh
r
rwh
DESCRIPTION
Reserved. Return zeros when read.
Advisory nonfatal error mask. This bit is set by default to enable compatibility with
software that does not comprehend role-based error reporting.
0 – Error condition is unmasked
1 – Error condition is masked
Replay timer timeout mask.
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
REPLAY_NUM rollover mask.
0 – Error condition is unmasked
1 – Error condition is masked
Bad DLLP error mask.
0 – Error condition is unmasked
1 – Error condition is masked
Bad TLP error mask.
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
Receiver error mask.
0 – Error condition is unmasked
1 – Error condition is masked
84
XIO3130 Configuration Register Space
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