XIO3130 Datasheet, PDF (60/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express x1 3-port fanout switch

XIO3130
SLLS693C – MAY 2007 – REVISED JUNE 2008
www.ti.com
4.2.57 Serial Bus Slave Address Register
The Serial Bus Slave Address register is used to indicate the address of the device being targeted by the
serial bus cycle. This register also indicates whether the cycle will be a read or a write cycle. Writing to
this register initiates the cycle on the serial interface. This register is reset with PERST. The default value
corresponds to a serial EEPROM slave address of 7’b101_0000.
PCI register offset:
B2h
Register type:
Read/Write
Default value:
A0h
BIT NUM BER
RESET STATE
76543210
10100000
Table 4-31. Bit Descriptions – Serial Bus Slave Address Register
BIT FIELD NAME ACCESS
DESCRIPTION
7:1 SLAVE_ADDR
Serial bus slave address. This bit field represents the slave address for a read/write transaction
rw
on the serial interface.
This field is reset with PERST.
Read/Write command. This bit is used to determine whether the serial bus cycle is a read or a
write cycle.
0
RW_CMD
rw
0 – A single byte write is requested.
1 – A single byte read is requested.
This field is reset with PERST.
4.2.58 Serial Bus Control and Status Register
The Serial Bus Control and Status register is used to control the behavior of the serial bus interface. This
register also provides status information about the state of the serial bus.
PCI register offset:
Register type:
Default value:
BIT NUMBER
7
RESET STATE
0
B3h
Read/Write; Read Only; Clear by a Write of One; Hardware Update
00h
6543210
0000000
Table 4-32. Bit Descriptions – Serial Bus Control and Status Register
BIT FIELD NAME
7
PROT_SEL
6
RSVD
5
REQBUSY
4
ROMBUSY
ACCESS
rw
r
ru
ru
DESCRIPTION
Protocol select. This bit is used to select the serial bus address mode used.
0 – Slave address and byte address are sent on the serial bus.
1 – Only the slave address is sent on the serial bus.
This field is reset with PERST.
Reserved. When read, this bit returns zero.
Requested serial bus access busy. This bit is set when a serial bus cycle is in progress.
0 – No serial bus cycle
1 – Serial bus cycle in progress
This field is reset with PERST.
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the XIO3130
device is downloading register defaults from a serial EEPROM.
0 – No EEPROM activity
1 – EEPROM download in progress
This field is reset with PERST.
60
XIO3130 Configuration Register Space
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