XIO3130 Datasheet, PDF (25/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express x1 3-port fanout switch

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Message
Assert_INTx
Deassert_INTx
PM_Active_State_Nak
PM_PME
PME_Turn_Off
PME_TO_Ack
ERR_COR
ERR_NONFATAL
ERR_FATAL
Unlock
Set_Slot_Power_Limit
Advanced Switching Messages
Vendor Defined Type 0
Vendor Defined Type 1
XIO3130
SLLS693C – MAY 2007 – REVISED JUNE 2008
Table 3-2. Messages Supported by the XIO3130
Supported
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
XIO3130 Action
Passed through upstream
Passed through upstream
Received and processed
Passed through upstream
Downstream PCI Hot Plug Event: Initiated upstream
Received and processed
Passed through downstream
Downstream port: Received and processed
Downstream ports: Initiated upstream
Passed through upstream
Initiated upstream
Passed through upstream
Initiated upstream
Passed through upstream
Initiated upstream
Received and processed
Passed through downstream
Upstream port: Received and processed
Downstream port: Initiated downstream
Discarded
Upstream port: Unsupported request
Passed through downstream
Upstream port: Discarded
Passed through downstream
All supported message transactions are processed according to the PCI Express Base Specification.
3.3 GPIO Terminals
Up to 19 general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals available varies based on the implementation of various supported
functions that share GPIO terminals. When any of the shared functions are enabled, the associated GPIO
terminal is disabled. When pulled high, the DPSTRP terminals cause some GPIO terminals to be mapped
to PCI Hot Plug functions for specific ports. Additional information can be found in the DPSTRP pin
descriptions and in Chapter 4.
All GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bits in the GPIOA, GPIOB, GPIOC, or GPIOD Control Registers. The GPIO data register is used to
monitor GPIO terminals defined as inputs or to set the state of GPIO terminals defined as outputs. For
more information on GPIO terminals, see sections Section 4.2.61 through Section 4.2.65.
3.4 Serial EEPROM
The XIO3130 provides a two-wire serial-bus interface to load subsystem identification information and
specific register defaults from an external EEPROM. This interface supports slow, fast, and high-speed
EEPROM speed options.
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