XIO3130 Datasheet, PDF (56/139 Pages) Texas Instruments – XIO3130 switch is a PCI Express x1 3-port fanout switch

XIO3130
SLLS693C – MAY 2007 – REVISED JUNE 2008
www.ti.com
Table 4-26. Bit Descriptions – Device Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
10
APPE
r
Auxiliary power PM enable. This bit is read-only zero, since the XIO3130 requires a minimal
amount of AUX power when PME is disabled.
9
PFE
r
Phantom function enable. Since the XIO3130 part does not support phantom functions, this bit
is read-only zero.
8
ETFE
r
Extended tag field enable. Since the XIO3130 part does not support extended tags, this bit is
read-only zero.
Max payload size. This field is programmed by the host software to set the maximum size of
posted writes or read completions that the XIO3130 can initiate. This field is encoded as:
000 – 128B
001 – 256B
7:5
MPS
010 – 512B
rw
011 – 1024B
100 – 2048B
101 – 4096B
110 – Reserved
111 – Reserved
4
ERO
r
Enable relaxed ordering. Since the XIO3130 part does not support relaxed ordering, this bit is
read-only zero.
3
URRE
Unsupported request reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when an unsupported request is received by
rw
the upstream port.
0 – Do not report unsupported requests to the root complex.
1 – Report unsupported requests to the root complex.
2
FERE
Fatal error reporting enable. If this bit is set, the XIO3130 is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
rw
0 – Do not report fatal errors to the root complex.
1 – Report fatal errors to the root complex.
1
NFERE
Nonfatal error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
rw
0 – Do not report nonfatal errors to the root complex.
1 – Report nonfatal errors to the root complex.
0
CERE
Correctable error reporting enable. If this bit is set, the XIO3130 is enabled to send
ERR_CORR messages to the root complex when a system error event occurs.
rw
0 – Do not report correctable errors to the root complex.
1 – Report correctable errors to the root complex.
4.2.51 Device Status Register
The Device Status register controls PCI Express device-specific parameters.
PCI register offset:
9Ah
Register type:
Read Only; Clear by a Write of One; Hardware Update
Default value:
00X0h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
BIT FIELD NAME
15:6
RSVD
5
PEND
Table 4-27. Bit Descriptions – Device Status Register
ACCESS
r
ru
DESCRIPTION
Reserved. When read, these bits return zeros.
Transaction PENDING. This bit is set when the XIO3130 has issued a non-posted transaction
that has not been completed yet.
56
XIO3130 Configuration Register Space
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