PCI1410 Datasheet, PDF (83/145 Pages) Texas Instruments – PC CARD CONTROLLERS

4.36 Socket DMA Register 1
The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA
transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI
I/O address space. See Table 4–14 for a complete description of the register contents.
NOTE:32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards
is 16 bits.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Socket DMA register 1
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Socket DMA register 1
Type
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31–16
15–4
3
2–1
0
Register:
Offset:
Type:
Default:
SIGNAL
RSVD
DMABASE
EXTMODE
XFERSIZE
DDMAEN
Socket DMA register 1
98h
Read-only, Read/Write
0000 0000h
TYPE
R
R/W
R
R/W
R/W
Table 4–14. Socket DMA Register 1
FUNCTION
Reserved. Bits 31–16 return 0s when read.
DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI
I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K
bytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode.
Thus, the window is aligned to a natural 16-byte boundary.
Extended addressing. This feature is not supported by the PCI4410 and always returns a 0.
Transfer size. Bits 2 and 1 specify the width of the DMA transfer on the PC Card interface and are
encoded as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
11 = Reserved
DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value
of bits 15–4 (DMABASE field).
0 = Disabled (default)
1 = Enabled
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