PCI1410 Datasheet, PDF(34/145 Page) Texas Instruments

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PCI1410 Datasheet, PDF (34/145 Pages) Texas Instruments – PC CARD CONTROLLERS

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Table 2â16. CardBus PC Card Interface Control Terminals

TERMINAL

NAME

NUMBER

I/O

GGU PGE GHK

DESCRIPTION

CAUDIO B5 134 C10

CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The

I PCI1410 supports the binary audio mode and outputs a binary signal from the card to

SPKROUT.

CBLOCK D11 103 E19 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.

CCD1

CCD2

L12 75 L19

A4 137 A9

CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1

I and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and

card type.

CardBus device select. The PCI1410 asserts CDEVSEL to claim a CardBus cycle as the target

CDEVSEL B13

107

E17

I/O device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL until a target

responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle

with an initiator abort.

CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is

CFRAME B11

111

E14

I/O asserted to indicate that a bus transaction is beginning, and data transfers continue while this

signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final

data phase.

CGNT

C11 106 F15

CardBus bus grant. CGNT is driven by the PCI1410 to grant a CardBus PC Card access to the

CardBus bus after the current data transaction has been completed.

CINT

D6 132 A10

CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing

from the host.

CIRDY

CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the

A12

110

C15

I/O

current data phase of the transaction. A data phase is completed on a rising edge of CCLK when

both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted,

wait states are inserted.

CPERR

C13 104 F14

CardBus parity error. CPERR reports parity errors during CardBus transactions, except during

I/O special cycles. It is driven low by a target two clocks following that data when a parity error is

detected.

CREQ

B8 123 E12

CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the

CardBus bus as an initiator.

CSERR

A5 133 B10

CardBus system error. CSERR reports address parity errors and other system errors that could

I lead to catastrophic results. CSERR is driven by the card synchronous to CCLK. The PCI1410

can report CSERR to the system by assertion of SERR on the PCI interface.

CSTOP

C12 105 E18

CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current

I/O CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by

target devices that do not support burst data transfers.

CSTSCHG C5 135 E10

CardBus status change. CSTSCHG alerts the system to a change in the card status, and is

used as a wake-up mechanism.

CTRDY

A13 109 A16

CardBus target ready. CTRDY indicates the ability of the CardBus target ability to complete the

I/O current data phase of the transaction. A data phase is completed on a rising edge of CCLK,

when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.

CVS1

CVS2

131 F11

117 E13

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in

I/O conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine

the operating voltage and card type.

2â20

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