TMS320F28044_10 Datasheet, PDF (82/115 Pages) Texas Instruments – Digital Signal Processor

TMS320F28044
SPRS357C – AUGUST 2006 – REVISED JANUARY 2010
V_DDIO, V_DD3VFL
V_DDA2, V_DDAIO
(3.3 V)
V_DD, V_DD1A18,
V_DD2A18
(1.8 V)
XCLKIN
X1/X2
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XCLKOUT
XRS
t_OSCST
t_w(RSL1)
OSCCLK/8^(A)
User-Code Dependent
Address/Data/
Control
(Internal)
Boot-Mode
Pins
Address/Data Valid. Internal Boot-ROM Code Execution Phase
t_d(EX)
t_{h(boot-mode)(B)}
GPIO Pins as Input
Boot-ROM Execution Starts
User-Code Execution Phase
User-Code Dependent
Peripheral/GPIO Function
Based on Boot Code
I/O Pins^(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-4. Power-on Reset
82
Electrical Specifications
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