TMS320VC5505 Datasheet, PDF (81/141 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5505
Fixed-Point Digital Signal Processor
SPRS503A – JUNE 2009 – REVISED JULY 2009
The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 4 chip selects,
along with memory control signals.
The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External
Bus Selection Register (EBSR). For more detail on the pin muxing, see the Section 4.6.1, External Bus
Selection Register (EBSR). For more information on the VC5505 EMIF, see the TMS320VC5505 DSP
External Memory Interface (EMIF) User's Guide (literature number SPRUFO8).
6.9.1 EMIF Asynchronous Memory Support
The EMIF supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address
lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF
(EM_CS[5:2]).
Each chip select has the following individually programmable attributes:
• Data bus width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes
6.9.2 EMIF Peripheral Register Description(s)
Table 6-11 shows the EMIF registers.
For more detailed information on the EMIF and its registers, see the TMS320VC5505 External Memory
Interface (EMIF) User's Guide (literature number SPRUFO8).
HEX ADDRESS
RANGE
1000h
1001h
1004h
1005h
1010h
1011h
1014h
1015h
1018h
1019h
101Ch
101Dh
1040h
1044h
Table 6-11. External Memory Interface (EMIF) Peripheral Registers⁽¹⁾
ACRONYM
REGISTER NAME
REV
STATUS
AWCCR1
AWCCR2
ACS2CR1
ACS2CR2
ACS3CR1
ACS3CR2
ACS4CR1
ACS4CR2
ACS5CR1
ACS5CR2
EIRR
EIMR
Revision Register
Status Register
Asynchronous Wait Cycle Configuration Register 1
Asynchronous Wait Cycle Configuration Register 2
Asynchronous CS2 Configuration Register 1
Asynchronous CS2 Configuration Register 2
Asynchronous CS3 Configuration Register 1
Asynchronous CS3 Configuration Register 2
Asynchronous CS4 Configuration Register 1
Asynchronous CS4 Configuration Register 2
Asynchronous CS5 Configuration Register 1
Asynchronous CS5 Configuration Register 2
EMIF Interrupt Raw Register
EMIF Interrupt Mask Register
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
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Peripheral Information and Electrical Specifications
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