TMS320VC5505 Datasheet, PDF (37/141 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320VC5505
Fixed-Point Digital Signal Processor
SPRS503A – JUNE 2009 – REVISED JULY 2009
Table 3-18. GPIO Terminal Functions (continued)
SIGNAL
NAME
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
LCD_D[2]/
GP[12]
P7 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 12 (GP[12]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[3]/
GP[13]
N7 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 13 (GP[13]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[4]/
GP[14]
N8 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 14 (GP[14]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[5]/
GP[15]
P9 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 15 (GP[15]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[6]/
GP[16]
N9 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 16 (GP[16]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[7]/
GP[17]
P10 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 17 (GP[17]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D8]/
I2S2_CLK/
GP[18]/
SPI_CLK
N10 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge and GPIO.
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
P11 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
N11 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between LCD Bridge, I2S2, GPIOand SPI.
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
EM_A[15]/GP[21] N1 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 21 (GP[21]).
Mux control via the A15_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EM_A[16]/GP[22] E2 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 22 (GP[22]).
Mux control via the A16_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EM_A[17]/GP[23] F2 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 23 (GP[23]).
Mux control via the A17_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EM_A[18]/GP[24] G2 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 24 (GP[24]).
Mux control via the A18_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EM_A[19]/GP[25] G4 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 25 (GP[25]).
Mux control via the A19_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EM_A[20]/GP[26] J3 I/O/Z
IPD
DV_DDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 26 (GP[26]).
Mux control via the A20_MODE bit in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
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