TMS320VC5505 Datasheet, PDF (1/141 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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1 Fixed-Point Digital Signal Processor
1.1 TMS320VC5505 Features
• High-Performance, Low-Power, TMS320C55x™
Fixed-Point Digital Signal Processor
– 16.67-, 10-ns Instruction Cycle Time
– 60-, 100-MHz Clock Rate
– One/Two Instruction(s) Executed per Cycle
– Dual Multipliers [Up to 200 Million
Multiply-Accumulates per Second
(MMACS)]
– Two Arithmetic/Logic Units (ALUs)
– Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses
– Fully Software-Compatible With C55x
Devices
– Industrial Temperature Devices Available
• 320K Bytes Zero-Wait State On-Chip RAM,
Composed of:
– 64K Bytes of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
– 256K Bytes of Single-Access RAM
(SARAM), 32 Blocks of 4K x 16-Bit
• 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
• 16-/8-Bit External Memory Interface (EMIF) with
Glueless Interface to:
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
– 8-/16-Bit NOR Flash
– Asynchronous Static RAM (SRAM)
• Direct Memory Access (DMA) Controller
– Four DMA With 4 Channels Each
(16-Channels Total)
• Three 32-Bit General-Purpose Timers
– One Selectable as a Watchdog and/or GP
• Two MultiMedia Card/Secure Digital (MMC/SD)
Interfaces
• Universal Asynchronous Receiver/Transmitter
(UART)
• Serial-Port Interface (SPI) With Four
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I²C
Bus™)
TMS320VC5505
Fixed-Point Digital Signal Processor
SPRS503A – JUNE 2009 – REVISED JULY 2009
• Four Inter-IC Sound (I²S Bus™) for Data
Transport
• Device USB Port With Integrated 2.0
High-Speed PHY that Supports:
– USB 2.0 Full- and High-Speed Device
• LCD Bridge With Asynchronous Interface
• Tightly-Coupled FFT Hardware Accelerator
• 10-Bit 4-Input Successive Approximation
(SAR) ADC
• Real-Time Clock (RTC) With Crystal Input, With
Separate Clock Domain, Separate Power
Supply
• Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
• Four I/O Isolated Power Supply Domains: RTC
I/O, EMIF I/O, USB PHY, and DV_DDIO
• Low-Power S/W Programmable Phase-Locked
Loop (PLL) Clock Generator
• On-Chip ROM Bootloader (RBL) to Boot From
NAND Flash, NOR Flash, SPI EEPROM, or I2C
EEPROM
• IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
• Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• 196-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZCH Suffix)
• 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
• 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
• Applications:
– Wireless Audio Devices (e.g., Headsets,
Microphones, Speakerphones, etc.)
– Echo Cancellation Headphones
– Portable Medical Devices
– Voice Applications
– Industrial Controls
– Fingerprint Biometrics
– Software Defined Radio
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Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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