TLK1521 Datasheet, PDF (8/19 Pages) Texas Instruments – 500 Mbps to 1.3 Gbps TRANSCEIVER

TLK1521
500 Mbps to 1.3 Gbps TRANSCEIVER
SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
NAME
NO.
SIGNAL PIN
DOUTTXP
60
DOUTTXN
59
DINRXP
54
DINRXN
53
GTX_CLK
8
TXD0
62
TXD1
63
TXD2
64
TXD3
2
TXD4
3
TXD5
4
TXD6
6
TXD7
7
TXD8
10
TXD9
11
TXD1
12
TXD11
14
TXD12
15
TXD13
16
TXD14
17
TXD15
19
TXD16
20
TXD17
22
RXD0
51
RXD1
50
RXD2
49
RXD3
47
RXD4
46
RXD5
45
RXD6
44
RXD7
42
RXD8
40
RXD9
39
RXD10
37
RXD11
36
RXD12
35
RXD13
34
RXD14
32
RXD15
31
RXD16
30
RXD17
29
RX_CLK
41
TYPE
DESCRIPTION
Output
(High-Z
power up)
Input
Input
Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to
copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK
value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are
active when LOOPEN is low. During power-on reset, these pins are high impedance.
Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface TXD. The frequency range of GTX_CLK is 25 MHz to 65 MHz. The transmitter uses the rising
edge of this clock to register the 18-bit input data (TXD) for serialization.
Input
Transmit data bus. These inputs carry the 18-bit parallel data output from a protocol device to the
transceiver for encoding, serialization and transmission. This 18-bit parallel data is clocked into the
transceiver on the rising edge of GTX_CLK as shown in Figure 6.
Output
(High-Z on
power up)
Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol
device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 7.
These pins are tri-stated during power-on reset.
Output (low Recovered clock. Output clock that is synchronized to RXD. RX_CLK is the recovered serial data rate
on power up) clock divided by 20. RX_CLK is held low during power-on reset.
8
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