TLK1521 Datasheet, PDF (5/19 Pages) Texas Instruments – 500 Mbps to 1.3 Gbps TRANSCEIVER

TLK1521
500 Mbps to 1.3 Gbps TRANSCEIVER
SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004
parallel-to-serial
The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the framing logic and
converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally
generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (TD0) is transmitted first as
shown in Figure 3.
high-speed data output
The high-speed data output driver consists of a PECL-compatible differential pair that can be optimized for a
particular transmission line impedance and length. The line can be directly coupled or ac coupled. See Figure 11
and Figure 12 for termination details. No external pullup or pulldown resistors are required.
The TLK1521 provides a selectable signal preemphasis option for driving lossy media. When signal
preemphasis is enabled, the first bit of a run length of same-value bits is driven to a larger output swing, which
precompensates for signal inter-symbol interference (ISI) in lossy media, such as copper cables or printed
circuit board traces.
receive interface
The receiver portion of the TLK1521 accepts 20-bit framed differential serial data. The interpolator and clock
recovery circuit locks to the data stream and extracts the bit rate clock. This recovered clock is used to retime
the input data stream. The serial data is then aligned to the 20-bit word boundary by finding the start/stop bits
and the 18-bit data is output on a 18-bit wide parallel bus synchronized to the extracted receive clock.
receive data bus
The receive bus interface drives 18-bit wide single-ended TTL parallel data at the RXD[0:17] pins. Data is valid
on the rising edge of RX_CLK. The RX_CLK is used as the recovered word clock. The data and clock signals
are aligned as shown in Figure 4. Detailed timing information can be found in the TTL output switching
characteristics table.
RX_CLK
RXDn
tsu
th
Figure 4. Receive Timing Waveform
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