TLK1521 Datasheet, PDF (7/19 Pages) Texas Instruments – 500 Mbps to 1.3 Gbps TRANSCEIVER

TLK1521
500 Mbps to 1.3 Gbps TRANSCEIVER
SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004
random lock synchronization (continued)
The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer
could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive
multitransition (RMT). This occurs when more than one low-high transition takes place per clock cycle over
multiple clock cycles. In the worst case, the deserializer could become locked to the data pattern rather than
the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the
circuitry prevents the LOCKB from becoming active until the potential false-lock pattern changes. Notice that
the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does
not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does
not go into lock until it finds a unique data boundary that consists of four consecutive start/stop bits at the same
position.
The deserializer stays in lock until it cannot detect the same data boundary (start/stop bits) for four consecutive
cycles. Then the deserializer goes out of lock and hunts for the new data boundary (start/stop bits). In the event
of loss of synchronization, the LOCKB pin output goes inactive and the outputs (including RX_CLK) enter a
high-impedance state. The user’s system should monitor the LOCKB pin in order to detect a loss of
synchronization. Upon detection of loss of lock, sending SYNC patterns for resynchronization is desirable if
reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as
previously noted. LOCKB is held inactive for at least nine cycles after loss of lock is detected.
recommended power-up sequence
When powering up the device, it is recommended to first set the ENABLE pin low. Set the ENABLE pin to high
once sufficient time has passed to allow the power supply to stabilize.
power-down mode
When the ENABLE pin is deasserted low, the TLK1521 goes into a power-down mode. In the power-down
mode, the serial transmit pins (DOUTTXP, DOUTTXN) and the receive data bus pins (RXD[0:17]) go into a
high-impedance state.
reference clock input
The reference clock (GTX_CLK) is an external input clock that synchronizes the transmitter interface. The
reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency locked to the reference clock and used to clock out the serial transmit data
on both its rising and falling edge clock providing a serial data rate that is 20 times the reference clock.
operating frequency range
The TLK1521 may operate at a serial data rate between 500 Mbit/s to 1.3 Gbit/s. GTX_CLK must be within ±100
PPM of the desired parallel data rate clock.
testability
The TLK1521 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The ENABLE pin allows for all circuitry to be disabled so
that an IDDQ test can be performed.
loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling
this pin causes serial transmitted data to be routed internally to the receiver. The parallel data output can be
compared to the parallel input data for functional verification. (The external differential output is held in a
high-impedance state during the loop-back testing.)
power-on reset
Upon application of minimum valid power, the TLK1521 generates a power-on reset. During the power-on reset,
the RXD pins are tri-stated and RX_CLK is held low. The length of the power-on reset cycle is dependent upon
the REFCLK frequency, but is less than 1 ms in duration.
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