TLK1521 Datasheet, PDF (4/19 Pages) Texas Instruments – 500 Mbps to 1.3 Gbps TRANSCEIVER

TLK1521
500 Mbps to 1.3 Gbps TRANSCEIVER
SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004
GTX_CLK
TXDn
tsu
th
Figure 1. Transmit Timing Waveform
transmission latency
The data transmission latency of the TLK1521 is defined as the delay from the initial 18-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
Figure 2 illustrates the timing relationship between the transmit data bus, GTX_CLK, and serial transmit pins.
DOUTTXP,
DOUTTXN
TXD(0−17)
td(Tx _latency)
16-Bit Word to Transmit
Transmitted 20-Bit Word
GTX_CLK
Figure 2. Transmitter Latency
start/stop framing logic
All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving
PLL has a minimal number of transitions in which to stay locked onto the data stream. The signal coding also
provides a mechanism for the receiver to identify the byte boundary for correct deserialization. The TLK1521
wraps a start bit (1) and a stop bit (0) around the 18-bit data payload as shown in Figure 3. This is transparent
to the user, as the TLK1521 internally adds the framing bits to the data such that the user reads and writes actual
18-bit data.
start/stop framing logic (continued)
Stop Start TD0 TD1
Bit Bit
...
TD16 TD17 Stop Start
Bit Bit
Figure 3. Serial Output Data Stream With Start and Stop Bit
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