SMJ320C40 Datasheet, PDF (8/62 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001
block diagram (continued)
PDATA Bus
PADDR Bus
DDATA Bus
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus
LD31–LD0
LA30–LA0
LDE
LAE
M
LSTAT3–LSTAT0
U
LLOCK
X
LSTRB0–LSTRB1
LR/W0–LR/W1
LPAGE0–LPAGE1
LRDY0–LRDY1
LCE0, LCE1
32
32
DMA Coprocessor
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
Six DMA Channels
MUX
32
COM Port 0
32
Input
FIFO
32
32 _Output
PAU
32
FIFO
Port Control Registers
32
P
e
r
i
p
h
e
r
a
l
D
a
t
a
B
u
s
P
e
r
i ₃₂
p
COM Port 5
h
e
32
r
a ³²
l
32
A
Input
FIFO
Output
FIFO
PAU
Port Control Registers
d 32
d
r
Timer 0
e 32 Global Control Register
s
s
B ³²
Time Period Register
Timer Counter Register
u
Timer 1
s _{32 Global Control Register}
Time Period Register
Timer Counter Register
32
Port Control
Global
Local
32
CREQ0
CACK0
CSTRB0
CRDY0
C0D7–C0D0
CREQ5
CACK5
CSTRB5
CRDY5
C5D7–C5D0
TCLK0
TCLK1
8
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