SMJ320C40 Datasheet, PDF (46/62 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001
timing parameters of IIOFx changing from input to output mode (see Figure 19)
NO.
1 td(H1L-IFIO)
Delay time, H1 low to IIOFx switching from input to output
320C40-40
320C40-50
MIN MAX
16
320C40-60
MIN MAX
14
UNIT
ns
Execution of
Load of IIOF
H3
H1
TYPE Bit
1
IIOFx pins
Figure 19. Change of IIOFx From Input to Output Mode
timing parameters for RESET (see Figure 20)
320C40-40 320C40-50 320C40-60
NO.
MIN MAX MIN MAX MIN MAX
1 tsu(RESET-CIL)
2.1 td(CIH-H1H)
2.2 td(CIH-H1L)
3 tsu(RESETH-H1L)
Setup time, RESET before CLKIN low
Delay time, CLKIN high to H1 high
Delay time, CLKIN high to H1 low
Setup time, RESET high before H1 low and
after ten H1 clock cycles
11 tc(CI)
2
12
2
12
13
11 tc(Cl)*
2
10
2
10
13
11 tc(Cl)*
2
10
2
10
13
4.1 td(CIH-H3L)
4.2 td(CIH-H3H)
5 tdis(H1H-DZ)
Delay time, CLKIN high to H3 low
Delay time, CLKIN high to H3 high
Disable time, H1 high to (L)Dx in
high-impedance state
2
12 2
10 2
10
2
12 2
10 2
11
13*
13*
13*
6 tdis(H3H-AZ)
Disable time, H3 high to (L)Ax in
high-impedance state
9*
9*
9*
7 td(H3H-CONTROLH)
Delay time, H3 high to control signals high
[low for (L)PAGEx]
9*
9*
9*
8 td(H1H-IACKH)
Delay time, H1 high to IACK high
9
tdis(RESETL-ASYNCHZ)
Disable time, RESET low to asynchronous
reset signals in the high-impedance state
9*
9*
9*
21*
21*
21*
10 td(RESETH-COMMH)
Delay time, RESET high to asynchronous reset
signals high
15*
15*
15*
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
46
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