SMJ320C40 Datasheet, PDF (47/62 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

PARAMETER MEASUREMENT INFORMATION
X2/CLKIN
1
RESET
2.2
(see Notes E and F)
2.1
3
H1
4.1
5
H3
(L)Dx
(see Note A)
Ten H1 Clock Cycles
Hi-Z
4.2
6
(L)Ax
(see Note B)
Hi-Z
7
Control Signals
(see Note C)
7
(L)PAGE0–(L)PAGE1
(see Note C)
8
IACK
9
Asynchronous Reset
Signals (see Note D)
Hi-Z
9
10
Asynchronous Reset
Signals (see Note E)
Hi-Z
NOTES: A. In this figure, (L)Dx includes D31–D0, LD31–D0, and CxD7–CxD0.
B. (L)Ax includes A30–A0 and LA30–LA0.
C. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3–(L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.
D. Asynchronous reset signals that go into high impedance after RESET goes low include TCLK0, TCLK1, IIOF3–IIOF0, and the communication-port control signals
CREQx, CACKy, CSTRBy, and CRDYx (where x = 0, 1, or 2, and y = 3, 4, or 5). (At reset, ports 0, 1, and 2 become outputs, and ports 3, 4, and 5 become inputs.)
E. Asynchronous reset signals that go to a high-logic level after RESET goes low include CREQy, CACKx, CSTRBx, and CRDYy (where x = 0, 1, or 2, and y = 3,
4, or 5).
F. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown will occur;
otherwise, an additional delay of one clock cycle can occur.
Figure 20. RESET Timing