DRV8809 Datasheet, PDF (8/44 Pages) Texas Instruments – COMBINATION MOTOR DRIVERS WITH DC-DC CONVERTERS

DRV8809
DRV8810
SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
T_J = 0°C to 120°C, V_M = 7 V to 40 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Charge-Pump VCP (＝_P = 0.1 µF to 0.47 µF, C_bk = 0.01 µF ± 10%)
V_O(CP)
Output voltage
I_LOAD = 0 mA,
V_M > VthV_M2
f_(CP)
Switching frequency
t_start
Start-up time
CStorage = 0.1 µF,
V_M ≥ 16 V
Internal Clock OSCi
MIN TYP
MAX UNIT
V_M + 10
V_M + 13 V
1.6
MHz
0.5
2 ms
f_OSCi
VREF Input
System clock frequency
5.76 6.4
7.04 MHz
V_REF
Reference voltage input
I_leak-vr
Input leak current
C_SELECT for DC-DC Start-Up Selection (DCDC_MODE = L)
0.8 2.5
3.6 V
1 µA
Vcs0
DC-DC all off
0
Vcs1
Turn on ODB then ODA
Pull down by external 200-kΩ resistor
1.3
0.3 V
2V
Vcs2
Turn on ODB then ODC
As pin open
3
3.3 V
C_SELECT for DC-DC Start-Up Selection (DCDC_MODE = H or Open, Ch-B/C Parallel Mode)
Vcs0
DC-DC all off
0
Vcs1
Turn on ODB/C then ODA
Pull down by external 200-kΩ resistor
1.3
0.3 V
2V
Vcs2
Turn on ODA then ODB/C
Three DC-DC Converters⁽²⁾
As pin open
3
3.6 V
V_DINOPE
ODA
ODB
ODC
Operating supply voltage
VoutA = 1.5 V – 30 V,
VoutB/C = 1.5 V – 10 V,
Programmable with external
reference on FBX
× VDIN > 1.25 × Vout (largest)
Ratio to V_OUT(DC)
20 V ≤ VDIN < 40 V
6.5 V ≤ VDIN < 20 V
Vth_VM– < VDIN < 6.5 V,
V_O ≤ 3.3 V
1.25 =
V_O
–3
V_O
–3
V_O
–3
V_O
V
3
5%
5
V_FB
I_{O ODx}
I_{O ODBC}
FBX feedback voltage
ODx output current (dc)
OD_BC output current (DC)
in Ch-B/Ch-C parallel mode
For ODA/B/C
With external L and C
With external L and C DCDC_MODE = H
1.50
V
1.5 A
3A
I_{O ODx2}
I_{O ODx3}
f_OSCD
R_ds(ON)
5 V-Low
Vo_min6
Output current (dc) at low VDIN
Output current (dc) at low VDIN
Switching (chopping frequency)
FET ON resistance at 0.8 A for
OD_x
5.5-V V_O at VDIN = VthV_
V_O voltage to 5.5 V
V_O voltage drop from VDIN
V_O setting without kick UVP
when VDIN = VthV_M+
(V_O setting at VDIN = 10 V)
VDIN = 7 V,
VDIN = 7 V,
f_OSCD = (0,0)
T_J = 25°C
T_J = 120°C
V_O = 5 V
V_O = 3.3 V
VDIN = VthV_, VthV_ = 5-V load (dc) = 0.5
A ⁽³⁾
VthV_M+ = 6-V load (DC) = 0.5 A⁽⁴⁾
90 100
0.35
4
–30
6
0.8 A
1.5 A
110 kHz
Ω
0.50
V
%
1V
V
(2) DCDC_MODE = H, Ch-B and Ch-C are in parallel driving mode.
(3) Lower VDIN decrease gate drive and the voltage drop is increased. Specified by bench characterization only.
(4) V_OUT (at VDIN = VthV_M+) is lower than V_O setting. When VDIN is down to VthV_M+, undervoltage protection (UVP) shuts down the
device, in case the V_O is set as V_O > 7 V. Specified by design.
8
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