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DRV8809 Datasheet, PDF (12/44 Pages) Texas Instruments – COMBINATION MOTOR DRIVERS WITH DC-DC CONVERTERS
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DRV8809
DRV8810
SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
Sixteen bits serial data is shifted into the least significant bit (LSB) of the serial data input (DATA) shift register
on the falling edge of the serial clock (CLK). After 16 bits of data transfer, the strobe signal (Strobe) rising edge
latches all the shifted data. During data transfer, Strobe voltage level is acceptable high or low.
DATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CLK
Strobe
Figure 3. Serial Interface
Setup Mode/Power-Down Mode
The motor output mode is configured through serial interface (DATA AB, CLK AB and STROBEAB) when
nSLEEP = L. After setup, the nSLEEP pin must be pulled high for normal motor drive control. The condition that
the device requires for setup (initialization) is after the nORT (Reset) output goes to high from the low level
(power on, recovery from VM < 7 V). While nSLEEP is low, all the motor drive functions are shut down and their
outputs are high-impedance state. Also the stepper parameters in the register are all reset to 0. This device
forces motor driver functions to shut down for the power-down mode, and it is not damaged even if nSLEEP is
asserted during motor driving. At the Strobe pulse rising edge, the DATA signal level must be low for normal
setup mode (see Extended Setup Mode for another option).
Extended Setup Mode
While nSLEEP = L, if the DATA signal level is set high when the Strobe pulse is set, the serial interface
recognizes the input data to set the extended setup mode. This extended setup register enables monitoring and
controlling the fault condition of this chip. One of the internal protection control signals is selected and provided
to LOGIC OUT pin. Also, this enables the application to ignore the protection control and/or suppress the reset
signal generation. This device has device ID (3-bit ROM) and vendor ID (1-bit ROM), which can be read out from
LOGIC OUT. Four bits are assigned to select the LOGIC OUT signal, including the ID ROM bit readout.
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