DRV8809 Datasheet, PDF (30/44 Pages) Texas Instruments – COMBINATION MOTOR DRIVERS WITH DC-DC CONVERTERS

DRV8809
DRV8810
SLVS854A – JULY 2008 – REVISED JULY 2008 ............................................................................................................................................................... www.ti.com
The regulator has a soft-start function to limit the rush current during start up. It is achieved by using VFB ramp
during soft start.
For unused DC-DC converter channels, the external components can be removed if the channel is set to inactive
by the C_SELECT pin and register bits. Also, the VFB pin can be left open or connected to ground.
DCDC_MODE selector can operate channel B and C in parallel mode to handle 2× output driving capability.
VFB_B pin is active for feedback, and VFB_C pin must be pulled down internally.
DCDC_MODE for Parallel-Mode Control
The DCDC_MODE pin selects the DC-DC converter parallel driving for Ch-B and Ch-C. The input is pulled up to
internal 3.3 V by a 200-kΩ resistor. When the pin is H or left open, Ch-B and Ch-C are driven in parallel.
C_SELECT
Gnd
Pull Down
(by external 200 kW)
OPEN
Table 16. C_SELECT for Start-Up
PIN VOLTAGE
0 V to 0.3 V
DC-DC Vout1,
ODA
OFF
DC-DC Vout2,
ODB
OFF
1.3 V to 2 V
See Table 17
3 V to 3.3 V
ON
ON
DC-DC Vout3,
ODC
OFF
ON
DCDC_MODE and C_SELECT Timing Delay and Start-Up Order
DCDC_MODE and C_SELECT play a role in the order of regulator enablement, as well as the time when the first
regulator is enabled to when the second is enabled. Regulators B and C are always enabled together, whether
they are working in parallel mode or not.
DCDC_MODE
L
L
L
H
H
H
Table 17. DCDC_MODE and C_SELECT Timing Delay (DRV8809)
C_SELECT
GND
Pull down
3 V to 3.3 V
GND
Pull down
3 V to 3.3 V
TIMING DELAY
None
None
1.6 ms
None
1.6 ms
1.6 ms
DESCRIPTION
No regulator is enabled.
No regulator is enabled.
Ch-A followed by Ch-B and Ch-C
No regulator is enabled.
Ch-B and Ch-C followed by Ch-A
Ch-A followed by Ch-B and Ch-C
DCDC_MODE
L
L
L
H
H
H
Table 18. DCDC_MODE and C_SELECT Timing Delay (DRV8810)
C_SELECT
GND
Pull down
3 V to 3.3 V
GND
Pull down
3 V to 3.3 V
TIMING DELAY
None
None
1.6 ms
None
20 ms to 40 ms
20 ms to 40 ms
DESCRIPTION
No regulator is enabled.
No regulator is enabled.
Ch-A followed by Ch-B and Ch-C
No regulator is enabled.
Ch-B and Ch-C followed by Ch-A
Ch-A followed by Ch-B and Ch-C
In-Reset: Input for System Reset
In-Reset pin assertion stops all the DC-DC converters and H-bridges. It also reset all the register contents to
default value. After deassertion of the input, the device follows the initial start-up sequence. The C_SELECT
state is captured after the In-Reset deassertion. The input is pulled up to internal 3.3 V by 200-kΩ resistor. When
the pin = H or left open, reset function is asserted. Also it has deglitch filter of 2.5 µs to 7.5 µs.
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