BQ4014_08 Datasheet, PDF (8/13 Pages) Texas Instruments – 256Kx8 Nonvolatile SRAM

bq4014/bq4014Y
Power-Down/Power-Up Cycle (TA = 0 to 70°C)
Symbol
Parameter
tPF
VCC slew, 4.75 to 4.25 V
tFS
VCC slew, 4.25 to VSO
tPU
VCC slew, VSO to VPFD (max.)
Minimum
300
10
0
tCER
Chip enable recovery time
40
Data-retention time in
tDR
absence of V_CC
10
tWPT
Write-protect time
40
Typical
-
-
-
80
-
100
Maximum
-
-
-
120
Unit
µs
µs
µs
ms
Conditions
Time during which
SRAM is write-protected
after VCC passes VPFD on
power-up.
-
years TA = 25°C. (2)
Delay after VCC slews
150
µs down past VPFD before
SRAM is write-protected.
Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Sept. 1992
8