BQ4014_08 Datasheet, PDF (6/13 Pages) Texas Instruments – 256Kx8 Nonvolatile SRAM

bq4014/bq4014Y
Write Cycle (TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tWC
Write cycle time
tCW
Chip enable to end of write
tAW
Address valid to end of write
tAS
Address setup time
tWP
tWR1
tWR2
tDW
tDH1
tDH2
tWZ
tOW
Write pulse width
Write recovery time
(write cycle 1)
Write recovery time
(write cycle 2)
Data valid to end of write
Data hold time
(write cycle 1)
Data hold time
(write cycle 2)
Write enabled to output in
high Z
Output active from end of
write
-85
-120
Min. Max. Min. Max. Units
Conditions/Notes
85 - 120 -
ns
75 - 100 -
ns
(1)
75 - 100 -
ns
(1)
Measured from address valid to
0
-
0
-
ns _{beginning of write. (2)}
65 - 85 -
Measured from beginning of write to
ns _{end of write. (1)}
Measured from WE going high to end
5
-
5
-
ns _{of write cycle. (3)}
15 - 15 -
Measured from CE going high to end
ns _{of write cycle. (3)}
35 - 45 -
Measured to first low-to-high
ns _{transition of either CE or WE.}
Measured from WE going high to end
0
-
0
-
ns _{of write cycle. (4)}
10 - 10 -
Measured from CE going high to end
ns _{of write cycle. (4)}
0 30 0 40 ns I/O pins are in output state. (5)
0
-
0
-
ns I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Sept. 1992
6