BQ4011 Datasheet, PDF (8/13 Pages) Texas Instruments – 32Kx8 Nonvolatile SRAM

bq4011/bq4011Y
Power-Down/Power-Up Cycle (TA = TOPR)
Symbol
Parameter
tPF
VCC slew, 4.75 to 4.25 V
tFS
VCC slew, 4.25 to VSO
tPU
VCC slew, VSO to VPFD (max.)
Minimum
300
10
0
Typical Maximum
-
-
-
-
-
-
tCER
Chip enable recovery time
40
80
120
tDR
tDR-N
Data-retention time in
absence of V_CC
Data-retention time in
absence of V_CC
10
-
-
6
-
-
tWPT
Write-protect time
40
100
150
Unit
µs
µs
µs
ms
years
years
µs
Conditions
Time during which SRAM is
write-protected after VCC
passes VPFD on power-up.
TA = 25°C. (2)
TA = 25°C (2); industrial
temperature range (-N) only.
Delay after VCC slews down
past VPFD before SRAM is
write-protected.
Notes: 1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Aug. 1993 C
8