BQ4011 Datasheet, PDF (4/13 Pages) Texas Instruments – 32Kx8 Nonvolatile SRAM

bq4011/bq4011Y
AC Test Conditions
Parameter
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
Test Conditions
0V to 3.0V
5 ns
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
tRC
Read cycle time
tAA
Address access time
tACE
Chip enable access time
Output enable to
tOE
output valid
Chip enable to output
tCLZ
in low Z
tOLZ
Output enable to
output in low Z
tCHZ
Chip disable to output
in high Z
tOHZ
Output disable to
output in high Z
Output hold from
tOH
address change
-70/-70N
-100
-150/-150N
-200
Min. Max. Min. Max. Min. Max. Min. Max.
70
- 100 - 150 - 200 -
-
70
- 100 - 150 - 200
-
70
- 100 - 150 - 200
-
35
-
50
-
70
-
90
5
-
5
-
10
-
10
-
5
-
5
-
5
-
5
-
0 25 0 40 0 60 0 70
0 25 0 35 0 50 0 70
10
-
10
-
10
-
10
-
Unit Conditions
ns
ns Output load A
ns Output load A
ns Output load A
ns Output load B
ns Output load B
ns Output load B
ns Output load B
ns Output load A
Aug. 1993 C
4