BQ4011 Datasheet, PDF (6/13 Pages) Texas Instruments – 32Kx8 Nonvolatile SRAM

bq4011/bq4011Y
Write Cycle (TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
-70/-70N
-100
-150/-150N
-200
Min. Max. Min. Max. Min. Max. Min. Max. _Units
Conditions/Notes
tWC
tCW
tAW
tAS
tWP
tWR1
tWR2
tDW
tDH1
tDH2
tWZ
tOW
Notes:
Write cycle time 70
Chip enable to
end of write
55
Address valid to
end of write
55
Address setup ₀
time
Write pulse
55
width
Write recovery
time (write
5
cycle 1)
Write recovery
time (write
15
cycle 2)
Data valid to end ₃₀
of write
Data hold time
(write cycle 1)
0
Data hold time
(write cycle 2)
0
Write enabled to
output in high Z ⁰
Output active
from end of write ⁵
- 100 - 150 - 200 -
- 90 - 100 - 150 -
- 80 - 90 - 150 -
-
0
-
0
-
0
-
- 75 - 90 - 130 -
-
5
-
5
-
5
-
- 15 - 15 - 15 -
- 40 - 50 - 70 -
-
0
-
0
-
0
-
-
0
-
0
-
0
-
25 0 35 0 50 0 70
-
5
-
5
-
5
-
ns
ns
(1)
ns
(1)
Measured from
ns address valid to
beginning of write. (2)
Measured from
ns beginning of write to
end of write. (1)
Measured from WE
ns going high to end of
write cycle. (3)
Measured from CE
ns going high to end of
write cycle. (3)
Measured from first
ns low-to-high transition
of either CE or WE.
Measured from WE
ns going high to end of
write cycle. (4)
Measured from CE
ns going high to end of
write cycle.(4)
I/O pins are in output
ns _{state. (5)}
I/O pins are in output
ns _{state. (5)}
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1993 C
6