BQ3285EC Datasheet, PDF (8/26 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285EC/LC
Power-Down/Power-Up Cycle
The bq3285EC and bq3285LC power-up/power-down cy-
cles are different. The bq3285LC continuously monitors
VCC for out-of-tolerance. During a power failure, when
VCC falls below VPFD (2.53V typical), the bq3285LC write-
protects the clock and storage registers. The power source
is switched to BC when VCC is less than VPFD and BC is
greater than VPFD, or when VCC is less than VBC and VBC
is less than VPFD. RTC operation and storage data are
sustained by a valid backup energy source. When VCC is
above VPFD, the power source is VCC. Write-protection con-
tinues for tCSR time after VCC rises above VPFD.
The bq3285EC continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285EC write-protects the
clock and storage registers. When VCC is below VBC (3V
typical), the power source is switched to BC. RTC opera-
tion and storage data are sustained by a valid backup
energy source. When VCC is above VBC, the power
source is VCC. Write-protection continues for tCSR time
after VCC rises above VPFD.
Control/Status Registers
The four control/status registers of the bq3285EC/LC
are accessible regardless of the status of the update cy-
cle (see Table 4).
Register A
Register A Bits
7
6
5
4
3
2
1
0
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
Register A programs:
n The frequency of the periodic event rate.
n Oscillator operation.
n Time-keeping
Register A provides:
n Status of the update cycle.
RS0–RS3 - Frequency Select
7
6
5
4
3
2
1
0
-
-
-
- RS3 RS2 RS1 RS0
These bits select the periodic interrupt rate, as shown in
Table 3.
OS0–OS2 - Oscillator Control
7
6
5
4
3
2
1
0
- OS2 OS1 OS0 -
-
-
-
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on for the bq3285LC and to ensure that the
bq3285EC/LC will keep time in battery-backup mode. A
pattern of 11X turns the oscillator on, but keeps the fre-
quency divider disabled. When 010 is written, the RTC
begins its first update after 500ms.
UIP - Update Cycle Status
7
6
5
4
3
2
1
0
UIP -
-
-
-
-
-
-
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
Table 4. Control/Status Registers
Reg.
A
Loc.
(Hex) Read Write _{7 (MSB)}
0A Yes Yes¹ UIP na
6
OS2 na
Bit Name and State on Reset
5
4
3
2
OS1 na OS0 na RS3 na RS2 na
1
RS1 na
0 (LSB)
RS0 na
B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 - 0 DF na HF na DSE na
C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - na - 0 - 0
D 0D Yes No VRT na - 0 - 0 - 0 - 0 - 0 - 0 - 0
Notes:
na = not affected.
1. Except bit 7.
July 1996
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