BQ3285EC Datasheet, PDF (3/26 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285EC/LC
DS
Data strobe input
When MOT = VCC, DS controls data trans-
fer during a bq3285EC/LC bus cycle. Dur-
ing a read cycle, the bq3285EC/LC drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
to latch write data into the chip.
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
R/W
Read/write input
When MOT = VCC, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
based system. The rising edge on R/W
latches data into the bq3285EC/LC.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285EC/LC.
INT
Interrupt request output
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
32K
32.768 kHz output
32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at
32.768kHz as long as VCC is valid.
EXTRAM Extended RAM enable
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30kΩ
pull-down resistor. To access the RTC regis-
ters, EXTRAM must be low.
RCL
BC
RST
X1–X2
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Us-
ing RAM clear does not affect the battery
load. This pin is connected internally to a
30kΩ pull-up resistor.
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of system power.
When VCC slews down past VBC (3V typi-
cal), the integral control circuitry switches
the power source to BC. When VCC returns
above VBC, the power source is switched to
VCC.
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
Reset input
The bq3285EC/LC is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285EC/LC is not ac-
cessible. Table 4 in the Control/Status Reg-
isters section lists the register bits that are
cleared by a reset.
Reset may be disabled by connecting RST
to VCC. This allows the control bits to re-
tain their states through power-
down/power-up cycles.
Crystal inputs
The X1–X2 inputs are provided for an ex-
ternal 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
July 1996
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