BQ3285EC Datasheet, PDF (10/26 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285EC/LC
Register C
Register C Bits
7
6
5
4
3
2
1
0
INTF PF AF UF 0
-
0
0
Register C is the read-only event status register.
Bits 0, 1, 2, 3 - Unused Bits
Register D
Register D Bits
7
6
5
4
3
2
1
0
VRT 0
0
0
0
0
0
0
Register D is the read-only data integrity status regis-
ter.
7
6
5
4
3
2
1
0
-
-
-
-
0
-
0
0
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
0
These bits are always set to 0.
UF - Update Event Flag
Bits 0–6 - Unused Bits
These bits are always set to 0.
7
6
5
4
3
-
-
- UF -
2
1
0
-
-
-
7
6
5
4
3
2
1
0
VRT -
-
-
-
-
-
-
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
AF - Alarm Event Flag
7
6
5
4
3
2
1
0
-
- AF -
-
-
-
-
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
VRT - Valid RAM and Time
1 = Valid backup energy source
0 = Backup energy source is depleted
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
PF - Periodic Event Flag
7
6
5
4
3
2
1
0
- PF -
-
-
-
-
-
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
INTF - Interrupt Request Flag
7
6
5
4
3
INTF -
-
-
-
2
1
0
-
-
-
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
PIE = 1 and PF = 1
UIE = 1 and UF = 1
Reading register C clears this bit.
July 1996
10