BQ3285EC Datasheet, PDF (2/26 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285EC/LC
Block Diagram
X1
Time-
Base
X2
Oscillator
÷8
÷ 64
÷ 64
3
4
16:1 MUX
RST
MOT
CS
R/W
µP
AS
Bus
AD0–AD7
I/F
DS
RCL
EXTRAM
VCC
BC
CS
Power-
Fail
Control
Control/Status
Registers
Clock/Calendar, Alarm
and Control Bytes
User Buffer
(14 Bytes)
Storage Registers
(114 Bytes)
Storage Registers
(128 Bytes)
VOUT
Write
Protect
32K
32K
Driver
Interupt
INT
Generator
Control/Calendar
Update
BD328501.eps
Pin Descriptions
MOT
Bus type select input
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
Ω resistor.
Table 1. Bus Setup
Bus MOT
DS
R/W
AS
Type Level Equivalent Equivalent Equivalent
Motorola
V_CC
DS, E, or
Φ2
R/W
AS
Intel
RD,
WR,
VSS MEMR, or MEMW, or ALE
I/OR
I/OW
AD0–AD7
AS
Multiplexed address/data
input/output
The bq3285EC/LC bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase pre-
cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7 and EXTRAM is latched into the
bq3285EC/LC on the falling edge of the AS
signal. During the data-transfer phase of
the bus cycle, the AD0–AD7 pins serve as a
bidirectional data bus.
Address strobe input
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD0–AD7 and EXTRAM. This de-
multiplexing process is independent of the
CS signal. For DIP and SOIC packages
with MOT = VSS, the AS input is provided a
signal similar to ALE in an Intel-based sys-
tem.
July 1996
2