ADS58H40_15 Datasheet, PDF (8/59 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

ADS58H40
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
PARAMETRIC MEASUREMENT INFORMATION
www.ti.com
LVDS OUTPUT TIMING
Figure 1 shows a timing diagram of the LVDS output voltage levels. Figure 2 shows the latency described in the
Timing Requirements table.
DxnP
Logic 0
V_ODL
Logic 1
V_ODH
DxnM
V_OCM
GND
Figure 1. LVDS Output Voltage Levels
Input
Signal
Input
Clock
CLKINM
CLKINP
DDR
LVDS
CLKOUTABM
(CLKOUTCDM)
CLKOUTABP
(CLKOUTCDP)
Output Data
DABP, DABM
(DCDP, DCDM)
Sample
N+1
N
t_A
N+2
N+3
N+4
N+10
N+11
N+12
t_PDI
Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A
(Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
Ch A Ch B Ch A Ch B Ch A Ch B Ch A Ch B Ch A
(Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
Figure 2. Latency Timing
8
Submit Documentation Feedback
Product Folder Links: ADS58H40
Copyright © 2012, Texas Instruments Incorporated