ADS58H40_15 Datasheet, PDF (40/59 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

ADS58H40
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
APPLICATION INFORMATION
www.ti.com
THEORY OF OPERATION
The ADS58H40 is a quad-channel, 11-bit, analog-to-digital converter (ADC) with sampling rates up to
250 MSPS. At every falling edge of the input clock, the analog input signal for each channel is sampled
simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each
stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference
(residue) between the stage input and its quantized equivalent is gained and propagates to the next stage. At
every clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from
all stages are combined in a digital correction logic block and digitally processed to create the final code, after a
data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential
signaling (LVDS) interface and is coded in binary twos complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 1.15 V, available on the
VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-V_PP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-Ω source drives the
ADC analog inputs.
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This configuration improves the
common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each
input pin is recommended to damp out ringing caused by package parasitics.
Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect
of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit).
Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant
part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling
circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.
Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low
source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance
path between the analog input pins and VCM is required from the common-mode switching currents perspective
as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode
voltage (VCM).
The ADS58H40 includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb
the sampling glitches inside the device itself. The R-C component values are also optimized to support high input
bandwidth (up to 500 MHz). However, using an R-LC-R filter (refer to Figure 46, Figure 47, Figure 48, Figure 49,
and Figure 50) improves glitch filtering, thus further resulting in better performance.
40
Submit Documentation Feedback
Product Folder Links: ADS58H40
Copyright © 2012, Texas Instruments Incorporated