ADS58H40_15 Datasheet, PDF (51/59 Pages) Texas Instruments – Quad-Channel, 250-MSPS Receiver and Feedback ADC

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ADS58H40
SBAS589B – AUGUST 2012 – REVISED NOVEMBER 2012
14-Bit Output in Burst Mode
(11-Bit in Default and SNRBoost^3G+
Mode on the Dxx[13:3] Output Pins)
CLKOUTxxP,
CLKOUTxxM
Dxx0P,
Dxx0M
Dxx1P,
Dxx1M
Dxx2P,
Dxx2M
Device
NOTE: xx = channels A and B or C and D.
CLKOUTABM
Figure 61. DDR LVDS Interface
Dxx12P,
Dxx12M
Dxx13P,
Dxx13M
CLKOUTABP
DAB[13:0]P,
DAB[13:0]M
CLKOUTCDM
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
Sample N
Sample N + 1
Sample N + 2
CLKOUTCDP
DCD[13:0]P,
DCD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
Sample N
Sample N + 1
Sample N + 2
Figure 62. DDR LVDS Interface Timing Diagram
Copyright © 2012, Texas Instruments Incorporated
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