LM4F232H5QCFIG Datasheet, PDF (783/1472 Pages) Texas Instruments – Stellaris® LM4F232H5QC Microcontroller

Stellaris^® LM4F232H5QC Microcontroller
Register 13: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034
This register is loaded with a match value. Interrupts can be generated when the timer value is equal
to the value in this register in one-shot or periodic mode.
In Edge-Count mode, this register along with GPTMTBILR, determines how many edge events are
counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this
value.
In PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM
signal.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this
register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register
return the current match value of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are
used for the match value. Bits 31:16 are reserved in both cases.
When a 32/64-bit Wide GPTM is configured to one of the 64-bit modes, GPTMTAMATCHR contains
bits 31:0 of the 64-bit match value and the GPTMTBMATCHR register contains bits 63:32.
GPTM Timer B Match (GPTMTBMATCHR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
32/64-bit Wide Timer 0 base: 0x4003.6000
32/64-bit Wide Timer 1 base: 0x4003.7000
32/64-bit Wide Timer 2 base: 0x4004.C000
32/64-bit Wide Timer 3 base: 0x4004.D000
32/64-bit Wide Timer 4 base: 0x4004.E000
32/64-bit Wide Timer 5 base: 0x4004.F000
Offset 0x034
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TBMR
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMR
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
1
Bit/Field
31:0
Name
TBMR
Type
Reset Description
R/W 0x0000.FFFF GPTM Timer B Match Register
(for 16/32-bit) _{This value is compared to the GPTMTBR register to determine match}
0xFFFF.FFFF _events.
(for 32/64-bit)
November 08, 2011
783
Texas Instruments-Advance Information