LM4F232H5QCFIG Datasheet, PDF (734/1472 Pages) Texas Instruments – Stellaris® LM4F232H5QC Microcontroller

General-Purpose Timers
(GPTMTBPR) register (see page 785), the GPTM Timer A Prescale Snapshot (GPTMTAPS) register
(see page 793), the GPTM Timer B Prescale Snapshot (GPTMTBPS) register (see page 794), the
GPTM Timer A Prescale Value (GPTMTAPV) register (see page 795), and the GPTM Timer B
Prescale Value (GPTMTBPV) register (see page 796).
11.3.2
Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 752). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers.
11.3.2.1
One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 754). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 762), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see “Wait-for-Trigger Mode” on page 743). Table 11-4 on page 734 shows the values that
are loaded into the timer registers when the timer is enabled.
Table 11-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Register
TnR
TnV
TnPS
TnPV
Count Down Mode
GPTMTnILR
GPTMTnILR
GPTMTnPR in individual mode; not available in
concatenated mode
GPTMTnPR in individual mode; not available in
concatenated mode
Count Up Mode
0x0
0x0
0x0 in individual mode; not available in
concatenated mode
0x0 in individual mode; not available in
concatenated mode
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start
value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
GPTMTnPR registers), the timer reloads with 0x0. If configured to be a one-shot timer, the timer
stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer,
the timer starts counting again on the next cycle.
In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is set in the GPTMTnMR
register), the value of the timer at the time-out event is loaded into the GPTMTnR register and the
value of the prescaler is loaded into the GPTMTnPS register. The free-running counter value is
shown in the GPTMTnV register and the free-running prescaler value is shown in the GPTMTnPV
register. In this manner, software can determine the time elapsed from the interrupt assertion to the
ISR entry by examining the snapshot values and the current value of the free-running timer. Snapshot
mode is not available when the timer is configured in one-shot mode.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS)
734
November 08, 2011
Texas Instruments-Advance Information