LM4F232H5QCFIG Datasheet, PDF (56/1472 Pages) Texas Instruments – Stellaris® LM4F232H5QC Microcontroller

Architectural Overview
1.3.3.4
I²C (see page 1022)
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I²C bus interfaces to external I²C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I²C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I²C bus can be designated as either a master or a slave. I²C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I²C master and slave can generate interrupts.
The LM4F232H5QC microcontroller includes six I²C modules with the following features:
■ Devices on the I²C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I²C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Clock low timeout interrupt
■ Dual slave address capability
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
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November 08, 2011
Texas Instruments-Advance Information