TMS320DM355_07 Datasheet, PDF (78/158 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B – SEPTEMBER 2007 – REVISED OCTOBER 2007
www.ti.com
• Power management
– Deep sleep and fast NAND boot control
• Bandwidth Management
– Bus master DMA priority control
For more information on the System Control Module refer to the ARM Subsystem User's Guide.
3.9 Pin Multiplexing
The DM355 makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. In order to accomplish this, pin multiplexing is controlled using
a combination of hardware configuration (at device reset) and software control. No attempt is made by the
DM355 hardware to ensure that the proper pin muxing has been selected for the peripherals or interface
mode being used, thus proper pin muxing configuration is the responsibility of the board and software
designers. An overview of the pin multiplexing is shown in Table 3-12.
Peripheral
VPFE (video in)
VPBE (video out)
AEMIF
ASP0
MMC/SD1
CLKOUT
I2C
UART1
SPI1
SPI0
Table 3-12. Peripheral Pin Mux Overview
Muxed With
GPIO and SPI2
GPIO, PWM, and RTO
GPIO
GPIO
GPIO and UART2
GPIO
GPIO
GPIO
GPIO
GPIO
Primary Function
VPFE (video in)
VPBE (video out)
AEMIF
ASP0
MMC/SD1
CLKOUT
I2C
UART1
SPI1
SPI0
Secondary Function
SPI2
PWM and RTO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Tertiary Function
GPIO
GPIO
none
none
UART2
none
none
none
none
none
3.9.1 Hardware Controlled Pin Multiplexing
Use the Asynchronous EMIF configuration pins (AECFG[3:0]) for hardware pin mux control. AECFG[3:0]
control the partitioning of the AEMIF addresses and GPIOs at reset, which allows you to properly
configure the number of AEMIF address pins required by the boot device while unused addresses pins are
available as GPIOs. These settings may be changed by software after reset by programming the PinMux2
register The PinMux2 register is in the System Control Module. As shown in Table 3-13, the number of
address bits enabled on the AEMIF is selectable from 0 to 16. Pins that are not assigned to another
peripheral and not enabled as address signals become GPIOs (except EM_A[2:1]). The enabled address
signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. The exception to this are
EM_A[2:1]. These signals (can be used to) represent the ALE and CLE signals for the NAND Flash mode
of the AEMIF and are always enabled. Note that EM_A[0] does not represent the lowest AEMIF address
bit. DM355 supports only 16-bit and 8-bit data widths for the AEMIF. In 16-bit mode, EM_BA[1] represents
the LS address bit (the half-word address) and EM_BA[0] represents the MS address bit (A[14]). In 8-bit
mode, EM_BA[1:0] represent the 2 LS address bits. Note that additional selections are available by
programming the PinMux2 register in software after boot. Note that AECFG selection of ‘0010’ selects
OneNAND interface. The AEMIF needs to operate in the half-rate mode (full_rate = 0) to meet frequency
requirements. Software should not change the PINMUX2 register setting to affect the AEMIF rate
operation. A soft reset of the AEMIF should be performed any time a rate change is made.
78
Detailed Device Description
Submit Documentation Feedback