TMS320DM355_07 Datasheet, PDF (21/158 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

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TERMINAL
NAME
NO.
DDR_A10
V6
DDR_A09
W6
DDR_A08
W5
DDR_A07
V5
DDR_A06
U5
DDR_A05
W4
DDR_A04
V4
DDR_A03
W3
DDR_A02
W2
DDR_A01
V3
DDR_A00
V2
DDR_DQ15 W17
DDR_DQ14 V16
DDR_DQ13 W16
DDR_DQ12 U16
DDR_DQ11 W15
DDR_DQ10 W14
DDR_DQ09 V14
DDR_DQ08 U13
DDR_DQ07 W13
DDR_DQ06 V13
DDR_DQ05 W12
DDR_DQ04 U12
DDR_DQ03 T11
DDR_DQ02 U11
DDR_DQ01 W11
DDR_DQ00 V11
DDR_
DQGATE0
W18
DDR_
DQGATE1
V17
DDR_VREF U10
V_{SSA_DLL}
V_{DDA33_DDR}
DLL
DDR_ZN
R11
R10
T9
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B – SEPTEMBER 2007 – REVISED OCTOBER 2007
Table 2-10. DDR Terminal Functions (continued)
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
V_{DD_DDR}
DDR Address Bus bit 10
DDR Address Bus bit 09
DDR Address Bus bit 08
DDR Address Bus bit 07
DDR Address Bus bit 06
DDR Address Bus bit 05
DDR Address Bus bit 04
DDR Address Bus bit 03
DDR Address Bus bit 02
DDR Address Bus bit 01
DDR Address Bus bit 00
DDR Data Bus bit 15
DDR Data Bus bit 14
DDR Data Bus bit 13
DDR Data Bus bit 12
DDR Data Bus bit 11
DDR Data Bus bit 10
DDR Data Bus bit 09
DDR Data Bus bit 08
DDR Data Bus bit 07
DDR Data Bus bit 06
DDR Data Bus bit 05
DDR Data Bus bit 04
DDR Data Bus bit 03
DDR Data Bus bit 02
DDR Data Bus bit 01
DDR Data Bus bit 00
DDR: Loopback signal for external DQS gating. Route to DDR and back to
DDR_DQGATE1 with same constraints as used for DDR clock and data.
DDR: Loopback signal for external DQS gating. Route to DDR and back to
DDR_DQGATE0 with same constraints as used for DDR clock and data.
DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of mDDR
an external resistor divider connected to this pin is necessary.
DDR: Ground for the DDR DLL
DDR: Power (3.3 V) for the DDR DLL
DDR: Reference output for drive strength calibration of N and P channel outputs.
Tie to ground via 50 ohm resistor @ 0.5% tolerance.
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