TMS320DM355_07 Datasheet, PDF (74/158 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B – SEPTEMBER 2007 – REVISED OCTOBER 2007
www.ti.com
3.6.2 PLLC1
PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1
registers. The following list, Table 3-10, and Figure 3-3 describe the customizations of PLLC1 in the
DM355.
• Provides primary DM355 system clock
• Software configurable
• Accepts clock input or internal oscillator input
• PLL pre-divider value is fixed to (/8)
• PLL multiplier value is programmable
• PLL post-divider
• Only SYSCLK[4:1] are used
• SYSCLK1 divider value is fixed to (/2)
• SYSCLK2 divider value is fixed to (/4)
• SYSCLK3 divider value is programmable
• SYSCLK4 divider value is programmable to (/4) or (/2)
• SYSCLKBP divider value is fixed to (/3)
• SYSCLK1 is routed to the ARM Subsystem
• SYSCLK2 is routed to peripherals
• SYSCLK3 is routed to the VPBE module
• SYSCLK4 is routed to the VPSS module
• AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1
• SYSCLKBP is routed to the output pin CLKOUT2
Output Clock
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
AUXCLK
SYSCLKBP
Table 3-10. PLLC1 Output Clocks
Used By
ARM Subsystem / MPEG and JPEG Co-Processor
Peripherals
VPBE (VENC module)
PLLDIV
Divider
/2
/4
/n
VPSS
Peripherals, CLKOUT1
CLKOUT2
/4 or /2
none
/3
Notes
Fixed divider
Fixed divider
Programmable divider (used to get 27
MHz for VENC)
Programmable divider
No divider
Fixed divider
74
Detailed Device Description
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