LM3S9781 Datasheet, PDF (712/1155 Pages) Texas Instruments – Stellaris® LM3S9781 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
I2C Slave Masked Interrupt Status (I2CSMIS)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x014
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
STOPMIS STARTMIS DATAMIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
0
Name
reserved
STOPMIS
STARTMIS
DATAMIS
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Stop Condition Masked Interrupt Status
Value Description
1 An unmasked STOP condition interrupt was signaled is pending.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR
register.
R/W
0
Start Condition Masked Interrupt Status
Value Description
1 An unmasked START condition interrupt was signaled is
pending.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR
register.
RO
0
Data Masked Interrupt Status
Value Description
1 An unmasked data received or data requested interrupt was
signaled is pending.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR
register.
712
June 29, 2010
Texas Instruments-Advance Information