LM3S9781 Datasheet, PDF (357/1155 Pages) Texas Instruments – Stellaris® LM3S9781 Microcontroller

Stellaris® LM3S9781 Microcontroller
0x3 for 256 MB. If using General-Purpose mode and no address at all, program the EPADR field
to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field
to 0x0 for 256 bytes.
8. To read or write directly, use the mapped address area (configured with the EPIADDRMAP
register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked
until the value is retrieved.
9. To perform a non-blocking read, see “Non-Blocking Reads” on page 355.
The following sub-sections describe the initialization and configuration for each of the modes of
operation. Care must be taken to initialize everything properly to ensure correct operation. Control
of the GPIO states is also important, as changes may cause the external device to interpret pin
states as actions or commands (see “Register Descriptions” on page 307). Normally, a pull-up or
pull-down is needed on the board to at least control the chip-select or chip-enable as the Stellaris^®
GPIOs come out of reset in tri-state.
10.4.1
SDRAM Mode
When activating the SDRAM mode, it is important to consider a few points:
1. Generally, it takes over 100 μs from when the mode is activated to when the first operation is
allowed. The SDRAM controller begins the SDRAM initialization sequence as soon as the mode
is selected and enabled via the EPICFG register. It is important that the GPIOs are properly
configured before the SDRAM mode is enabled, as the EPI controller is relying on the GPIO
block's ability to drive the pins immediately. As part of the initialization sequence, the LOAD
MODE REGISTER command is automatically sent to the SDRAM with a value of 0x27, which
sets a CAS latency of 2 and a full page burst length.
2. The INITSEQ bit in the EPI Status (EPISTAT) register can be checked to determine when the
initialization sequence is complete.
3. When using a frequency range and/or refresh value other than the default value, it is important
to configure the FREQ and RFSH fields in the EPI SDRAM Configuration (EPISDRAMCFG)
register shortly after activating the mode. After the 100-μs startup time, the EPI block must be
configured properly to keep the SDRAM contents stable.
4. The SLEEP bit in the EPISDRAMCFG register may be configured to put the SDRAM into a
low-power self-refreshing state. It is important to note that the SDRAM mode must not be
disabled once enabled, or else the SDRAM is no longer clocked and the contents are lost.
The SIZE field of the EPISDRAMCFG register must be configured correctly based on the amount
of SDRAM in the system.
The FREQ field must be configured according to the value that represents the range being used.
Based on the range selected, the number of external clocks used between certain operations (for
example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used,
then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower
frequency is given, incorrect operation occurs.
See “External Peripheral Interface (EPI)” on page 1090 for timing details for the SDRAM mode.
10.4.1.1
External Signal Connections
Table 10-3 on page 358 defines how EPI module signals should be connected to SDRAMs. The
table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use
June 29, 2010
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