XIO2001_101 Datasheet, PDF (7/131 Pages) Texas Instruments – PCI Express™ to PCI Bus Translation Bridge

XIO2001
www.ti.com
SCPS212D – MAY 2009 – REVISED JANUARY 2010
List of Tables
2-1 Power Supply Terminals ........................................................................................................ 15
2-2 Ground Terminals ................................................................................................................ 16
2-3 Combined Power Output Terminals ........................................................................................... 16
2-4 PCI Express Terminals .......................................................................................................... 16
2-5 PCI System Terminals........................................................................................................... 17
2-6 JTAG Terminals .................................................................................................................. 19
2-7 Miscellaneous Terminals ........................................................................................................ 20
3-1 XIO2001 Reset Options ......................................................................................................... 24
3-2 Initial Flow Control Credit Advertisements .................................................................................... 26
3-3 Messages Supported by the Bridge ........................................................................................... 26
3-4 IRQ Interrupt to MSI Message Mapping....................................................................................... 29
3-5 Classic PCI Arbiter Registers................................................................................................... 30
3-6
Type 0 Configuration Transaction
IDSEL Mapping................................................................................................................... 31
3-7 Interrupt Mapping In The Code Field .......................................................................................... 32
3-8 EEPROM Register Loading Map............................................................................................... 37
3-9 Registers Used To Program Serial-Bus Devices............................................................................. 39
3-10 Clocking In Low Power States.................................................................................................. 41
4-1 Classic PCI Configuration Register Map ...................................................................................... 42
4-2 Command Register Description ............................................................................................... 44
4-3 Status Register Description .................................................................................................... 45
4-4 Class Code and Revision ID Register Description .......................................................................... 46
4-5 Device Control Base Address Register Description ........................................................................ 48
4-6 I/O Base Register Description ................................................................................................. 49
4-7 I/O Limit Register Description .................................................................................................. 49
4-8 Secondary Status Register Description ...................................................................................... 50
4-9 Memory Base Register Description ........................................................................................... 51
4-10 Memory Limit Register Description ............................................................................................ 51
4-11 Prefetchable Memory Base Register Description ........................................................................... 52
4-12 Prefetchable Memory Limit Register Description ............................................................................ 52
4-13 Prefetchable Base Upper 32-Bit Register Description ...................................................................... 52
4-14 Prefetchable Limit Upper 32-Bit Register Description ...................................................................... 53
4-15 I/O Base Upper 16-Bit Register Description ................................................................................. 53
4-16 I/O Limit Upper 16-Bit Register Description .................................................................................. 54
4-17 Bridge Control Register Description ........................................................................................... 55
4-18 Power Management Capabilities Register Description ..................................................................... 59
4-19 Power Management Control/Status Register Description .................................................................. 59
4-20 PM Bridge Support Extension Register Description ........................................................................ 60
4-21 MSI Message Control Register Description .................................................................................. 61
4-22 MSI Message Lower Address Register Description ........................................................................ 62
4-23 MSI Message Data Register Description ..................................................................................... 62
4-24 PCI Express Capabilities Register Description .............................................................................. 63
4-25 Device Capabilities Register Description ..................................................................................... 64
4-26 Device Control Register Description .......................................................................................... 65
4-27 Device Status Register Description ........................................................................................... 66
4-28 Link Capabilities Register Description ........................................................................................ 67
4-29 Link Control Register Description ............................................................................................. 67
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List of Tables
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