XIO2001_101 Datasheet, PDF (66/131 Pages) Texas Instruments – PCI Express™ to PCI Bus Translation Bridge

XIO2001
SCPS212D – MAY 2009 – REVISED JANUARY 2010
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Table 4-26. Device Control Register Description (continued)
BIT
FIELD NAME
1
NFERE
0
CERE
ACCESS
RW
RW
DESCRIPTION
Nonfatal error reporting enable. If this bit is set, then the bridge is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
0 = Do not report nonfatal errors to the root complex (default)
1 = Report nonfatal errors to the root complex
Correctable error reporting enable. If this bit is set, then the bridge is enabled to send
ERR_COR messages to the root complex when a system error event occurs.
0 = Do not report correctable errors to the root complex (default)
1 = Report correctable errors to the root complex
4.51 Device Status Register
The device status register provides PCI Express device specific information to the system. See Table 4-27
for a complete description of the register contents.
PCI register offset:
Register type:
7Ah
Read-only
Default value:
0000h
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-27. Device Status Register Description
BIT
FIELD NAME ACCESS
DESCRIPTION
15:6 RSVD
R
Reserved. Returns 00 0000 0000b when read.
5
PEND
RU Transaction pending. This bit is set when the bridge has issued a non-posted transaction that
has not been completed.
4
APD
RU AUX power detected. This bit indicates that AUX power is present.
0 = No AUX power detected
1 = AUX power detected
3
URD
RCU
Unsupported request detected. This bit is set by the bridge when an unsupported request is
received.
2
FED
RCU Fatal error detected. This bit is set by the bridge when a fatal error is detected.
1
NFED
RCU Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.
0
CED
RCU Correctable error detected. This bit is set by the bridge when a correctable error is detected.
4.52 Link Capabilities Register
The link capabilities register indicates the link specific capabilities of the bridge. See Table 4-28 for a
complete description of the register contents.
PCI register offset:
Register type:
Default value:
7Ch
Read-only
000Y XC11h
BIT NUMBER
RESET STATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
y
y
BIT NUMBER
RESET STATE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
y
x
x
x
1
1
0
0
0
0
0
1
0
0
0
1
66
Classic PCI Configuration Space
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